1. Field of the Invention
The present technology relates to an integrated circuit with a clock circuit, tolerant to variations such as temperature, ground noise, and power noise.
2. Description of Related Art
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Because these variations affect the final timing of the output clock signal, various approaches address the variations in order to generate a uniform output clock signal despite the variations.
For example, U.S. Pat. No. 7,142,005 by Gaboury seeks to decouple power fluctuations from the clock signal, by adding buffer circuits with active loads, independent bias circuitry, and bias circuitry. These relatively complicated buffer circuits devote significantly more die area, and cost, to isolating such power fluctuations from the clock circuit.
In another example, the clock circuit of an integrated circuit relies on a reference signal generated by a combination of a voltage pump generating a high voltage in excess of a voltage supply, and a voltage regulator. Such circuitry consumes a great deal of layout area, and also consumes high current.
What is needed is an approach to address such variations with reduced complexity and cost.